The present invention relates generally to microprocessor architecture, and more particularly to the architecture of a microprocessor execution unit which performs arithmetic and logic operations concurrently with address computations.
Many modern microprocessors have a "pipelined architecture" whereby the processor is divided into stages. This permits the processor to perform several tasks at once thereby allowing the processor to work on different parts of the instructions simultaneously as they are advanced through the pipe with each clock cycle. Under ideal conditions, one instruction can leave the pipeline and another instruction enter the pipeline every clock cycle. One such microprocessor is the Intel486.TM. microprocessor. Compatible x86-type microprocessors include those made by Advanced Micro Devices and Cyrix.
Arising out of the need for compatibility with older Intel microprocessor designs and the fact that it is a general purpose microprocessor, the x86 microprocessor has a complex instruction set architecture which includes over 400 instructions. However, some of these instructions are rarely used by either the operating system or the compiler. Thus, it would be desirable to optimize the architecture for commonly used instructions.
As described in Chapter 2 of the "Intel486.TM. MICROPROCESSOR FAMILY PROGRAMMER'S REFERENCE MANUAL," the memory of an x86-type microprocessor is organized as a sequence of 8-bit bytes and each byte is assigned a unique physical address. However, application programs do not directly address the physical address, but instead use a virtual addressing scheme whereby the physical address is calculated based on a memory management model that includes segmentation and paging.
The physical memory is divided into independent memory spaces called segments. Each segment has a segment descriptor which contains its base address and a size limit for that segment. An application program issues a logical address which the addressing hardware translates into a linear address by adding an offset to the segment base address, so long as the offset does not exceed the size limit. The offset is the sum of three components, namely, a displacement value, a base register and an index register.
Paging is also supported by x86-type architecture, whereby linear address space, which may be part of physical memory or disk storage, is divided into 4k blocks of memory called pages. If paging is employed, addressing hardware translates the linear address into a physical address. If not, the linear address is the same as the physical address.
Thus, x86-type addressing hardware must handle the worst case scenario, namely, wherein the effective address is the sum of the base and all offset components. However, in many applications, only one offset component is present. Therefore, it would also be desirable to optimize the addressing hardware to handle the usual rather than the worst case addressing computation.